This invention relates generally to semiconductor memories such as static and dynamic random access memories, and more particularly the invention relates to the numbering sequence of memory arrays for faster selection of the shared sense amplifier regions between memory arrays.
Data is stored in semiconductor memories in addressable word lines with each word line having a plurality of data bits. The capacity of semiconductor memory integrated circuits has reached multi-mega bit levels, and the memory is organized as a plurality of addressable arrays for accessing stored data and writing data. As shown in FIG. 1, the memory arrays 10-1, 10-3, 10-5, 10-7 have sense amplifiers and input/output (I/O) circuitry 12-0, 12-2, 12-4, 12-6, 12-8 positioned above and below each array and shared by adjacent arrays. Each sense amplifier and I/O circuit is selected if and only if the memory array directly above or below the sense amplifier is selected. The activation of each block of sense amplifiers and I/O circuitry 12 requires the OR gating of the adjacent array select activation signals. The array select activation signals in FIG. 1, i.e. the outputs of inverters 15-1, 15-3, 15-5, 15-7, are ORed together in adjacent pairs to generate the sense amplifier and I/O activation signals i.e. the outputs of inverters 18-2, 18-4, 18-6. With this prior art implementation, the sense amplifier select signal occurs later than do the array select activation signals, that is, later than desirable. The binary coded numbering of arrays in accordance with the prior art does not allow for a direct AND gating of array select address signals to generate the sense amplifier activation signal because a plurality of bits might change between the two numbers. For example, array 1 (binary 001) and array 2 (binary 010) have both of the two least significant bits change between the two binary numbers. Thus, the decoding logic for controlling the shared block of sense amplifiers and I/O circuitry 12-4 requires two AND functions, NAND gates 14-3 and 14-5 followed by inverters which then feed a two input OR function, NOR gate 16-4 and inverter 18-4 to select and enable the block 12-4. Increased delay is encountered in the decoding operation.
The present invention is directed to an improved method of choosing the address decode sequence of memory arrays to allow for faster decoding of the shared sense amplifier and I/O regions between the memory arrays.